Non-volatile memory cells such as EEPROM cells typically have a double-layer polycrystalline silicon (“poly”) structure that includes a control gate layer and a floating gate layer. In contrast, semiconductor logic gates, having a control gate only, require only a single polysilicon process to form the control gate layer. To improve computing speed and reduce device size, non-volatile memory cells are sometimes embedded into logic chips. Since processes for forming a non-volatile memory cell and a logic gate are quite different, they are traditionally formed in a separate series of steps.
To reduce a total number of processing steps for a non-volatile memory embedded logic circuit, it is often desirable to form the embedded non-volatile memory cells using a single-layer poly structure. FIG. 1A shows a cross-section of a typical single-layered EEPROM cell 10 dissected along a wordline. FIG. 1B shows a cross-section of the same EEPROM cell 10 dissected along a bitline. With reference to FIG. 1A, a P-channel single poly EEPROM cell 10 is formed in an N-well 14 provided within a P-substrate. With reference to FIG. 1B, the EEPROM cell 10 includes a P-channel select transistor 24 and a P channel storage transistor 26. A first P+diffusion region 28 serves as both a drain for storage transistor 26 and a source for select transistor 24, and a second P+ diffusion region 30, which is coupled to a bitline 36, serves as a drain for select transistor 24. The single-layer polysilicon 20 serves as a floating gate for the storage transistor 26 and a select gate for the select transistor 24. Referring back to FIG. 1A, an application of a bias voltage to a control gate 12 enhances a channel 22 (FIG. 1B) extending between a source 32 and the drain 28 of storage transistor 26, and an application of a bias voltage to the select gate 24 enhances a channel 34 between the source 28 and the drain 30 of select transistor 24.
Referring again to FIG. 1A, a P-type buried diffusion layer serves as the control gate 12 for the EEPROM cell 10. A layer of silicon oxide 18 that is approximately 350 Å thick is provided between the floating gate 20 and the control gate 12. A tunnel oxide layer 16 that is about 70 Å thick lies between the floating gate 20 and the N-well 14. The single-poly silicon EEPROM cell 10 is programmed, erased, and read in a manner similar to that of a double-poly silicon cell. That is, programming is accomplished by electron tunneling from the floating gate 20 to the substrate 14 through the tunnel oxide 16 while erasing is realized by electrons tunneling from the substrate 14 to the floating gate 20.
Although the single poly silicon process described above allows the formation of a single polysilicon layer for both the floating gates of non-volatile memory cells and the control gates of the logic cells in the same step, the oxide layer underneath the polysilicon layer has to be formed in separate steps because its thickness varies throughout the embedded circuit. For instance, the thickness of a typical gate oxide layer for a low voltage logic gate is approximately 130 Å for 5 V systems, 50 Å for 2.5 V systems and 30 Å for 1.8 V systems. On the other hand, the tunnel oxide layer and the oxide layer between the floating gate and the control gate of a EEPROM cell is typically around 70 Å thick. Because the oxide layer thickness of the logic cells and the EEPROM cells are so different, they are typically formed in separate steps. For instance, U.S. Pat. No. 6,238,979 to Bergemont teaches an embedment of EEPROM cells in a logic device by forming the EEPROM cells first, followed by masking the completed EEPROM cells to form logic gates. It would be desirable to have an embedded circuit structure and a method for forming the structure that would allow the formation of the oxide layer for both the logic gate and the non-volatile memory cell in one step, thereby eliminating the need to form the EEPROM cells and the logic gates separately.